Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era

Electrothermal couplings between supply voltage, operating frequency, power dissipation and die temperature have been shown to significantly impact the energy-delay-product (EDP) based simultaneous optimization of supply (Vdd) and threshold (Vth) voltages. We present for the first time, the implications of an electrothermally aware EDP optimization on circuit operation in leakage dominant nanometer scale CMOS technologies. It is demonstrated that electrothermal EDP (EEDP) optimization restricts the operation of the circuit to a certain region in the Vdd-Vth plane. Also, the significance of EEDP optimization has been shown to increase with increase in leakage power and/or process variations.

[1]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[2]  Christer Svensson,et al.  Trading speed for low power by choice of supply and threshold voltages , 1993 .

[3]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[4]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[5]  Vivek De,et al.  Simultaneous power supply, threshold voltage, and transistor size optimization for low-power operation of CMOS circuits , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[6]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[7]  Vivek De,et al.  Technology and design challenges for low power and high performance [microprocessors] , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[8]  T. Sakurai,et al.  Optimization of V/sub DD/ and V/sub TH/ for low-power and high-speed applications , 2000, Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106).

[9]  Sheng-Chih Lin,et al.  A self-consistent junction temperature estimation methodology for nanometer scale ICs with implications for performance and thermal management , 2003, IEEE International Electron Devices Meeting 2003.

[10]  James Tschanz,et al.  Parameter variations and impact on circuits and microarchitecture , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[11]  K. Banerjee,et al.  Impact of off-state leakage current on electromigration design rules for nanometer scale CMOS technologies , 2004, 2004 IEEE International Reliability Physics Symposium. Proceedings.

[12]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .