Hierarchical Fault Response Modeling of Analog/RF Circuits

[1]  Abhijit Chatterjee,et al.  Fault-based automatic test generator for linear analog circuits , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[2]  Guido Gronthoud,et al.  Functional vs. multi-VDD testing of RF circuits , 2005, IEEE International Conference on Test, 2005..

[3]  Fang Liu,et al.  Efficient simulation of parametric faults for multi-stage analog circuits , 2007, 2007 IEEE International Test Conference.

[4]  M. W. Tian,et al.  Worst case tolerance analysis of linear analog circuits using sensitivity bands , 2000 .

[5]  Bozena Kaminska,et al.  Multifrequency testability analysis for analog circuits , 1994, Proceedings of IEEE VLSI Test Symposium.

[6]  Niels C. Lind,et al.  Methods of structural safety , 2006 .

[7]  David H. Evans An Application of Numerical Integration Techniclues to Statistical Toleraucing , 1967 .

[8]  Hans G. Kerkhoff,et al.  Fast fault simulation for nonlinear analog circuits , 2003, IEEE Design & Test of Computers.

[9]  Fang Liu,et al.  Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling , 2008, TODE.

[10]  John R. D'Errico,et al.  Statistical tolerancing using a modification of Taguchi's method , 1988 .

[11]  PETER J. ROUSSEEUW,et al.  Computing LTS Regression for Large Data Sets , 2005, Data Mining and Knowledge Discovery.

[12]  Genichi Taguchi,et al.  Performance analysis design , 1978 .

[13]  Bozena Kaminska,et al.  Analog circuit fault diagnosis based on sensitivity computation and functional testing , 1992, IEEE Design & Test of Computers.

[14]  Yiorgos Makris,et al.  Non-RF to RF Test Correlation Using Learning Machines: A Case Study , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[15]  M. Hubert,et al.  High-Breakdown Robust Multivariate Methods , 2008, 0808.0657.

[16]  Jean Charles Gilbert,et al.  Numerical Optimization: Theoretical and Practical Aspects , 2003 .

[17]  Abhijit Chatterjee,et al.  Alternate Test of RF Front Ends with IP Constraints: Frequency Domain Test Generation and Validation , 2006, 2006 IEEE International Test Conference.

[18]  Keith A. Jenkins,et al.  On-chip spectrum analyzer for analog built-in self test , 2005, 23rd IEEE VLSI Test Symposium (VTS'05).

[19]  Salvador Mir,et al.  Evaluation of Analog/RF Test Measurements at the Design Stage , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Fang Liu,et al.  Test yield estimation for analog/RF circuits over multiple correlated measurements , 2007, 2007 IEEE International Test Conference.

[21]  Brown,et al.  Defect Level as a Function of Fault Coverage , 1981, IEEE Transactions on Computers.

[22]  Fang Liu,et al.  Hierarchical analysis of process variation for mixed-signal systems , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[23]  Bozena Kaminska,et al.  Analog circuit testing based on sensitivity computation and new circuit modeling , 1993, Proceedings of IEEE International Test Conference - (ITC).

[24]  David Blaauw,et al.  Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations , 2003, ICCAD 2003.

[25]  C.-J. Richard Shi,et al.  Rapid frequency-domain analog fault simulation under parameter tolerances , 1997, DAC.

[26]  Xin Li,et al.  Robust analog/RF circuit design with projection-based posynomial modeling , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..

[27]  Guoyong Shi,et al.  Efficient DC fault simulation of nonlinear analog circuits: one-step relaxation and adaptive simulation continuation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  L. S. Milor,et al.  A tutorial introduction to research on analog and mixed-signal circuit testing , 1998 .

[29]  Sule Ozev,et al.  Dynamic test scheduling for analog circuits for improved test quality , 2008, 2008 IEEE International Conference on Computer Design.

[30]  Stephen K. Sunter,et al.  Test metrics for analog parametric faults , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).