17.6 1V 10Gb/s/pin single-ended transceiver with controllable active-inductor-based driver and adaptively calibrated cascade-DFE for post-LPDDR4 interfaces

Performance improvements in mobile devices with multi-cores and enhanced graphics quality requires higher memory bandwidth. Consequently, the design of I/O becomes a crucial issue [1]. In the LPDDR interface, a ground-terminated interface is used for a low-noise termination voltage (Vss) and small I/O capacitance (CIO) [2,3]. Even through noise margins and power efficiency are enhanced by ground termination, to compensate channel loss, the I/O is still the most power-hungry block. The pre-emphasized output driver and DFE are widely used to remove ISI and maximize read/write margins. However, multiple-taps in the output driver and the DFE are required to cover the channel loss, and they degrade the power efficiency of the I/O and occupy a large area.

[1]  Hyoung-Joo Kim,et al.  25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[2]  Byungsub Kim,et al.  A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[3]  Yi Lu,et al.  A 6.4Gb/s near-ground single-ended transceiver for dual-rank DIMM memory interface systems , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[4]  Yi Lu,et al.  A 6.4-Gb/s Near-Ground Single-Ended Transceiver for Dual-Rank DIMM Memory Interface Systems , 2014, IEEE Journal of Solid-State Circuits.

[5]  Chulwoo Kim,et al.  An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[6]  M. Nagata,et al.  A built-in technique for probing power supply and ground noise distribution within large-scale digital integrated circuits , 2005, IEEE Journal of Solid-State Circuits.