From Plasma to BeeFarm: Design Experience of an FPGA-Based Multicore Prototype

In this paper, we take a MIPS-based open-source uniprocessor soft core, Plasma, and extend it to obtain the Beefarm infrastructure for FPGA-based multiprocessor emulation, a popular research topic of the last few years both in the FPGA and the computer architecture communities. We discuss various design tradeoffs and we demonstrate superior scalability through experimental results compared to traditional software instruction set simulators. Based on our experience of designing and building a complete FPGA-based multiprocessor emulation system that supports run-time and compiler infrastructure and on the actual executions of our experiments running Software Transactional Memory (STM) benchmarks, we comment on the pros, cons and future trends of using hardware-based emulation for research.

[1]  Joel Emer,et al.  Implementing a Functional / Timing Partitioned Microprocessor Simulator with an FPGA , 2006 .

[2]  José Manuel Ferrández Vicente,et al.  Hand-based Interface for Augmented Reality. Poster , 2007 .

[3]  John Wawrzynek,et al.  RAMP Blue: A Message-Passing Manycore System in FPGAs , 2007, 2007 International Conference on Field Programmable Logic and Applications.

[4]  Mateo Valero,et al.  EazyHTM: EAger-LaZY hardware Transactional Memory , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[5]  David A. Wood,et al.  LogTM: log-based transactional memory , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[6]  Kunle Olukotun,et al.  Programming with transactional coherence and consistency (TCC) , 2004, ASPLOS XI.

[7]  Mark L. Chang,et al.  Low-Cost Stereo Vision on an FPGA , 2007 .

[8]  Ney Calazans,et al.  ACCELERATING SORTING WITH RECONFIGURABLE HARDWARE , 2000 .

[9]  Arvind,et al.  Bounded Dataflow Networks and Latency-Insensitive circuits , 2009, 2009 7th IEEE/ACM International Conference on Formal Methods and Models for Co-Design.

[10]  Torvald Riegel,et al.  Dynamic performance tuning of word-based software transactional memory , 2008, PPoPP.

[11]  D. B. Davis,et al.  Intel Corp. , 1993 .

[12]  Christoforos Kachris,et al.  Configurable Transactional Memory , 2007, 15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007).

[13]  J. Gregory Steffan,et al.  Application-specific signatures for transactional memory in soft processors , 2011, TRETS.

[14]  David A. Patterson,et al.  RAMP gold: An FPGA-based architecture simulator for multiprocessors , 2010, Design Automation Conference.

[15]  Kunle Olukotun,et al.  A practical FPGA-based framework for novel CMP research , 2007, FPGA '07.

[16]  Babak Falsafi,et al.  A complexity-effective architecture for accelerating full-system multiprocessor simulations using FPGAs , 2008, FPGA '08.

[17]  Kunle Olukotun,et al.  ATLAS: A Chip-Multiprocessor with Transactional Memory Support , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[18]  Dam Sunwoo,et al.  RAMP-White : An FPGA-Based Coherent Shared Memory Parallel Computer Emulator , 2007 .

[19]  Roberto A. Hexsel,et al.  A minimalist cache coherent MPSoC designed for FPGAs , 2011, Int. J. High Perform. Syst. Archit..

[20]  Kunle Olukotun,et al.  STAMP: Stanford Transactional Applications for Multi-Processing , 2008, 2008 IEEE International Symposium on Workload Characterization.

[21]  David I. August,et al.  Exploiting parallelism and structure to accelerate the simulation of chip multi-processors , 2006, The Twelfth International Symposium on High-Performance Computer Architecture, 2006..

[22]  Ronald G. Dreslinski,et al.  The M5 Simulator: Modeling Networked Systems , 2006, IEEE Micro.

[23]  Chen Chang,et al.  BEE3: Revitalizing Computer Architecture Research , 2009 .