The Basic Model of Attack Resistance Estimation for Monitoring the Program Code Integrity of the FPGA-Based Systems

An approach to monitoring the program code integrity of FPGA-based systems is considered. The approach is based on the use of a digital watermark to store monitoring information. As part of this approach, an integrity monitoring method is considered, which is characterized by the use of several rounds of the embedding of a digital watermark in a program code. A basic model for estimation the complexity of the attack on the integrity monitoring method is proposed. The model takes into account the possible directions of attack, both related to the storage of monitoring information in the form of a digital watermark, and the direction of attack due to the traditional mechanisms for protection of the method. With the help of the proposed model, the stages of the attack, which appear during the transition from traditional methods of storing control information to its storage in the form of a digital watermark, are shown.

[1]  Richard Hawkins,et al.  Software safety: relating software assurance and software integrity , 2010, Int. J. Crit. Comput. Based Syst..

[2]  Stephen D. Wolthusen,et al.  Techniques and Applications of Digital Watermarking and Content Protection , 2003, Artech House computer security series.

[3]  Swarup Bhunia,et al.  Hardware IP Security and Trust , 2017 .

[4]  Kapil Juneja,et al.  FRAME SELECTIVE AND DYNAMIC PATTERN BASED MODEL FOR EFFECTIVE AND SECURE VIDEO WATERMARKING , 2019, International Journal of Computing.

[5]  Martin Steinebach,et al.  Leakage detection and tracing for databases , 2013, IH&MMSec '13.

[6]  Jessica Fridrich.  Steganography in Digital Media: Preface , 2009 .

[7]  A. Drozd,et al.  Green Experiments with FPGA , 2017 .

[8]  Hideharu Amano,et al.  Principles and Structures of FPGAs , 2018, Springer Singapore.

[9]  Volodymyr Turchenko,et al.  Intelligent distributed sensor network , 1998, IMTC/98 Conference Proceedings. IEEE Instrumentation and Measurement Technology Conference. Where Instrumentation is Going (Cat. No.98CH36222).

[10]  John R. Vacca.  Computer and Information Security Handbook, Second Edition , 2013 .

[11]  Alexander V. Drozd,et al.  Hardware check of arithmetic devices with abridged execution of operations , 1996, Proceedings ED&TC European Design and Test Conference.

[12]  Giorgio Di Natale,et al.  Hardware Security and Trust: Design and Deployment of Integrated Circuits in a Threatened Environment , 2017 .

[13]  Donald G. Bailey,et al.  Design for Embedded Image Processing on FPGAs , 2011 .

[14]  Alexander Barkalov,et al.  Synthesis and Optimization of FPGA-Based Systems , 2014 .

[15]  David Kleidermacher,et al.  Embedded Systems Security: Practical Methods for Safe and Secure Software and Systems Development , 2012 .

[16]  Lucio Grandinetti,et al.  Technique of learning rate estimation for efficient training of MLP , 2000, Proceedings of the IEEE-INNS-ENNS International Joint Conference on Neural Networks. IJCNN 2000. Neural Computing: New Challenges and Perspectives for the New Millennium.

[17]  Alexander V. Drozd,et al.  Use of Natural LUT Redundancy to Improve Trustworthiness of FPGA Design , 2016, ICTERI.

[18]  Vyacheslav Kharchenko,et al.  Green computing and communications in critical application domains: Challenges and solutions , 2013, The International Conference on Digital Technologies 2013.

[19]  P. P. Deepthi,et al.  An Integrity Verification System for Images Using Hashing and Watermarking , 2012, 2012 International Conference on Communication Systems and Network Technologies.

[20]  Frank Y. Shih,et al.  Digital Watermarking and Steganography: Fundamentals and Techniques , 2007 .

[21]  Debdeep Mukhopadhyay,et al.  Hardware Security - Design, Threats, and Safeguards , 2014 .

[22]  B.K. Yi,et al.  Digital signatures , 2006, IEEE Potentials.

[23]  Valeria Garofalo,et al.  Truncated Binary Multipliers with minimum Mean Square Error: analytical characterization, circuit implementation and applications , 2009 .

[24]  Axel Sikora,et al.  INTEGRATION OF HARDWARE SECURITY MODULES INTO A DEEPLY EMBEDDED TLS STACK , 2016 .

[25]  Xiaomei Zhang,et al.  Research on the Hash Function Structures and its Application , 2017, Wirel. Pers. Commun..

[26]  Ashok B. Mehta.  ASIC/SoC Functional Design Verification , 2018 .

[27]  William Stallings,et al.  Cryptography and Network Security: Principles and Practice , 1998 .

[28]  Eduardo de la Torre Arnanz,et al.  FPGAs: Fundamentals, Advanced Features, and Applications in Industrial Electronics , 2017 .