论文信息 - A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.

[1] Amir M. Sodagar,et al. Mapping from phase to sine-amplitude in direct digital frequency synthesizers using parabolic approximation , 2000 .

[2] H. Samueli,et al. The optimization of direct digital frequency synthesizer performance in the presence of finite word length effects , 1988, Proceedings of the 42nd Annual Frequency Control Symposium, 1988..

[3] A.M. Fahim,et al. Low-power direct digital frequency synthesis for wireless communications , 2000, IEEE Journal of Solid-State Circuits.

[4] Venceslav F. Kroupa. CMOS/SOS Frequency Synthesizer LSI Circuit for Spread Spectrum Communications , 1999 .

[5] E.K.F. Lee,et al. A ROM-less direct digital frequency synthesizer using segmented nonlinear digital-to-analog converter , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[6] E.K.F. Lee,et al. Design of low-power ROM-less direct digital frequency synthesizer using nonlinear digital-to-analog converter , 1999, IEEE J. Solid State Circuits.