Thermal methodology for evaluating the performance of microelectronic devices with non-uniform power dissipation

Non-uniform power consumption across different functional units is commonly found in the contemporary microprocessor architectures. In such integrated circuit (IC) design, certain regions of the chip can dissipate a significant fraction of the total power while other regions of the die may dissipate little or no power. This non-uniformity of power dissipation results in non-uniform die temperature distribution with localized hot spots that may exceed the critical operating junction temperature (T/sub j/) and severely affect the microprocessor performance, production yield as well as product reliability. This trend directly drives an increasing importance of investigating thermal interactions of heat sources in the silicon chip. An important area of research is on the development of a methodology for evaluating the thermal impact of the non-uniform power concentration in microelectronic devices. The objective of this paper is to present the thermal analyses carried out to investigate the applicability of the superposition concept for predicting the temperature distribution of the silicon chip with non-uniform power dissipation patterns. In this investigation, the average chip temperature due to multiple heat sources within the silicon chip was defined as the reference temperature for evaluating the Tj rise of the particular chip segment. Verification of the methodology was carried out using the results obtained from finite element analysis (FEA). A heat sink thermal design was modeled to simulate a typical thermal design of a microprocessor. Key thermal parameters investigated are the heat source placement distance, convection heat transfer mode, and level of heat dissipation. Results of the verification show that the proposed approach offers a practical methodology for the thermal evaluation of microelectronic packages with nonuniform power dissipation.