Analysis of Safety Related Architectures

Fault and Error latency have a great impact on the dependability properties of control systems for critical applications. The replication techniques that are used to build such systems and the degree of replication usually are tailored to the tolerance of one fault (at a time) and result inadequate to cope with latent errors that show up altogether. For this reason, internal error detection mechanisms are coupled with on-line testing activities (diagnostic tests) intended to stress each component of the system so to induce errors and thus to anticipate their detection (reducing latency). Different testing strategies can be adopted on the basis of the element to be tested, the fault to be ‘hunted’, the characteristics of the system it is applied to. In this work we start from this simple consideration and will elaborate on architectural organizations to ensure safe and available service.

[1]  Georgi Gaydadjiev,et al.  March LA: a test for linked memory faults , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[2]  Dhiraj K. Pradhan,et al.  A METHOD FOR VM-IDATING COMPUTER-SYSTEM DEPENDABILITY , 1995 .

[3]  Peter Muhmenthaler,et al.  Enhanced fault modeling for DRAM test and analysis , 1991, Digest of Papers 1991 VLSI Test Symposium 'Chip-to-System Test Concerns for the 90's.

[4]  Paolo Prinetto,et al.  On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications , 1996, EDCC.

[5]  A. J. van de Goor,et al.  Testing Semiconductor Memories: Theory and Practice , 1998 .

[6]  Jacob A. Abraham,et al.  Efficient Algorithms for Testing Semiconductor Random-Access Memories , 1978, IEEE Transactions on Computers.

[7]  Brian Randell,et al.  Fundamental Concepts of Dependability , 2000 .

[8]  Ad J. van de Goor,et al.  Industrial evaluation of DRAM SIMM tests , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).

[9]  Janusz Sosnowski In-system testing of cache memories , 1995, Proceedings of 1995 IEEE International Test Conference (ITC).