A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits
暂无分享,去创建一个
[1] P. R. Stephan,et al. SIS : A System for Sequential Circuit Synthesis , 1992 .
[2] C. E. Clark. The Greatest of a Finite Set of Random Variables , 1961 .
[3] David Blaauw,et al. Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[4] Sarma B. K. Vrudhula,et al. A methodology to improve timing yield in the presence of process variations , 2004, Proceedings. 41st Design Automation Conference, 2004..
[5] Rob A. Rutenbar,et al. Static statistical timing analysis for latch-based pipeline designs , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[6] Natesan Venkateswaran,et al. First-Order Incremental Block-Based Statistical Timing Analysis , 2006, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[7] Kaushik Roy,et al. Novel sizing algorithm for yield improvement under process variation in nanometer technology , 2004, Proceedings. 41st Design Automation Conference, 2004..
[8] Youn-Long Lin,et al. Storage optimization by replacing some flip-flops with latches , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.
[9] K. Ravindran,et al. First-Order Incremental Block-Based Statistical Timing Analysis , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Jens Vygen,et al. Cycle time and slack optimization for VLSI-chips , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).
[11] Trevor N. Mudge,et al. CheckT/sub c/ and minT/sub c/: timing verification and optimal clocking of synchronous digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.
[12] Jeng-Liang Tsai,et al. A yield improvement methodology using pre- and post-silicon statistical clock scheduling , 2004, IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004..
[13] Robert K. Brayton,et al. Computing Clock Skew Schedules Under Normal Process Variation , 2005 .
[14] Vladimir Zolotov,et al. Gate sizing using incremental parameterized statistical timing analysis , 2005, ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005..
[15] Eby G. Friedman,et al. Optimal clock skew scheduling tolerant to process variations , 1996, DAC '96.
[16] Jing-Yang Jou,et al. On computing the minimum feedback vertex set of a directed graph bycontraction operations , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[17] Marios C. Papaefthymiou,et al. Fixed-phase retiming for low power design , 1996, ISLPED '96.