Digital pulse width modulator circuit capable of reducing power consumption and chip area

The invention belongs to the technical field of integrated circuit design, in particular to a digital pulse width modulator circuit capable of reducing power consumption and chip area, which is composed of a loop oscillator, a digital phase-locked loop controller, a pulse output circuit and the like. The pulse output circuit comprises two multi-channel selectors and a remote sensing (RS) trigger. The loop oscillator comprises a plurality of digital control delay unit and an inverter, the output of each delay unit is connected to the multi-channel selectors, the multi-channel selectors are selected according to input digital control bits, and the output of the multi-channel selectors trigger the RS trigger, thereby obtaining pulse signals with the required width. Compared with a general digital pulse width modulator, the digital pulse width modulator circuit reduces required delay units, thereby being capable of reducing the power consumption and the area.