A 43 mW single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS

A low-power small-area single-channel 4GS/s 4-bit flash ADC in 0.18 μm CMOS is presented. The entire ADC is implemented using CML blocks. To enhance the speed, both analog (comparators) and digital (encoder) parts of the ADC are fully pipelined. Furthermore, a reformulation for the encoder logic functions is introduced to reduce the wiring delay in the layout. The ADC achieves a figure of merit of 2.14 pJ/conversion-step. The ADC area including the resistor ladder is 0.06 mm2 and the power consumption is 43 mW when supplied with 1.8 V.

[1]  Yorgos Palaskas,et al.  A 4GS/S 4b flash ADC in 0.16μm CMOS , 2006 .

[2]  Edgar Sanchez-Sinencio,et al.  A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC , 2003 .

[3]  M. F. Wagdy,et al.  Determining ADC effective number of bits via histogram testing , 1991 .

[4]  Behzad Razavi,et al.  Principles of Data Conversion System Design , 1994 .

[5]  I. Mehr,et al.  A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications , 1998 .

[6]  Michael P. Flynn,et al.  A low-power 8-PAM serial-transceiver in 0.5 μm digital CMOS , 2001 .

[7]  A. Hastings.  The Art of Analog Layout , 2000 .

[8]  Randall L. Geiger,et al.  A 9b 165MS/s 1.8V pipelined ADC with all digital transistors amplifier , 2003, Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003..

[9]  E. Sackinger,et al.  A 3-GHz 32-dB CMOS limiting amplifier for SONET OC-48 receivers , 2000, IEEE Journal of Solid-State Circuits.

[10]  D. Draxelmayr,et al.  A 6b 600MHz 10mW ADC array in digital 90nm CMOS , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[11]  Walt Kester,et al.  The data conversion handbook , 2005 .

[12]  B. Wooley,et al.  A 40-GHz-bandwidth, 4-bit, time-interleaved A/D converter using photoconductive sampling , 2003, IEEE J. Solid State Circuits.

[13]  M. Tiebout,et al.  A 4GS/s 6b flash ADC in 0.13 /spl mu/m CMOS , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).

[14]  Ardie G. W. Venes,et al.  An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing , 1996 .

[15]  W. Liu,et al.  Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[16]  M. P. Flynn,et al.  Digital calibration incorporating redundancy of flash ADCs , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[17]  W. C. Black,et al.  A 900 MS/s 6b interleaved CMOS flash ADC , 2001, Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169).

[18]  Robert M. R. Neff,et al.  A 4 Gsample/s 8b ADC in 0.35 μm CMOS , 2002 .

[19]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .

[20]  David A. Patterson,et al.  Computer Architecture: A Quantitative Approach , 1969 .

[21]  Shanthi Pavan,et al.  A Dual-Mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D Converter in a 0.25- m Digital CMOS Process , 2000 .

[22]  C. Inui,et al.  60GHz CMOS Current-Reuse Cascade Amplifier , 2007, 2007 Asia-Pacific Microwave Conference.

[23]  Xicheng Jiang,et al.  A 2GS/s 6b ADC in 0.18μm CMOS , 2003 .

[24]  G. Geelen,et al.  A 6 b 1.1 GSample/s CMOS A/D converter , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[25]  Shin-Il Lim,et al.  A 4-bit 1.356 Gsps ADC for DS-CDMA UWB System , 2006, 2006 IEEE Asian Solid-State Circuits Conference.

[26]  S. Tsukamoto,et al.  A CMOS 6b 400 M sample/s ADC with error correction , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[27]  Shahriar Mirabbasi.  A 43mW Single-Channel 4GSIs4-Bit Flash ADC in O.18(pm CMOS , 2007 .

[28]  S. Mirabbasi,et al.  A 0.18 /spl mu/m CMOS pipelined encoder for a 5 GS/s 4-bit flash analogue-to-digital converter , 2005, Canadian Journal of Electrical and Computer Engineering.

[29]  A. Matsuzawa,et al.  A 6 b 800 MSample/s CMOS A/D converter , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[30]  A. Abidi,et al.  A 3 . 3V 12b 50-MS / s A / D Converter in 0 . 6-m CMOS with over 80-dB SFDR , 2000 .

[31]  Thomas Krause,et al.  A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[32]  Michael P. Flynn,et al.  A "digital" 6-bit ADC in 0.25-μm CMOS , 2002 .

[33]  Y. Tamba,et al.  A CMOS 6 b 500 MSample/s ADC for a hard disk drive read channel , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).

[34]  N. Krishnapura,et al.  A 5Gb/s NRZ transceiver with adaptive equalization for backplane transmission , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[35]  Boris Murmann,et al.  Digitally Assisted Analog Integrated Circuits , 2004, ACM Queue.

[36]  C.L. Portmann,et al.  Power-efficient metastability error reduction in CMOS flash A/D converters , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..

[37]  Behzad Razavi.  Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[38]  Geert Van der Plas,et al.  A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[39]  A. Matsuzawa,et al.  A mixed-signal 0.18-/spl mu/m CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM , 2001 .

[40]  K. Kattmann,et al.  A Technique For Reducing Differential Non-linearity Errors In Flash A/D Converters , 1991, 1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[41]  Michiel Steyaert,et al.  Speed-power-accuracy tradeoff in high-speed CMOS ADCs , 2002 .

[42]  Hui Pan,et al.  Spatial filtering in flash A/D converters , 2003 .

[43]  K. Yip,et al.  Clock tree distribution , 1997, IEEE Potentials.

[44]  Michael P. Flynn,et al.  A 3.5 GS/s 5-b Flash ADC in 90 nm CMOS , 2006, IEEE Custom Integrated Circuits Conference 2006.