Experimental Evidence for a New Single-Event Upset (SEU) Mode in a CMOS SRAM Obtained from Model Verification

Modeling of SEU has been done in a CMOS static RAM containing one-micron channel-length transistors fabricated from a P-well epilayer process using both circuit-and numerical-simulation techniques. The modeling results have been experimentally verified with the aid of heavy-ion beams obtained from a three-stage tandem van de Graaff accelerator. Experimental evidence for a new SEU mode in an on n-channel device is presented.

[1]  H. L. Grubin,et al.  Simulation of Charge Collection in a Multilayer Device , 1985, IEEE Transactions on Nuclear Science.

[2]  T. R. Oldham,et al.  Charge Collection Measurements for Heavy Ions Incident on n- and p-Type Silicon , 1983, IEEE Transactions on Nuclear Science.

[3]  A. B. Campbell,et al.  Charge Collection in Multilayer Structures , 1984, IEEE Transactions on Nuclear Science.

[4]  R. R. O'Brien,et al.  Collection of charge from alpha-particle tracks in silicon devices , 1983, IEEE Transactions on Electron Devices.

[5]  P. Thieberger,et al.  Single-Event Upset (SEU) Model Verification and Threshold Determination Using Heavy Ions in a Bipolar Static RAM , 1985, IEEE Transactions on Nuclear Science.

[6]  H. T. Weaver,et al.  Two-Dimensional Simulation of Single Event Indujced Bipolar Current in CMOS Structures , 1984, IEEE Transactions on Nuclear Science.