Energy-efficient higher-side-reset-and-set switching scheme for SAR ADC

A high energy-efficiency higher-side-reset-and-set (HSRS) switching scheme for a successive approximation register (SAR) ADC is presented, which consumes zero switching energy for the decision of the first two most significant bits without using any auxiliary circuit. The proposed HSRS scheme achieves 92.2% savings in switching energy and 50% reduction in total capacitance compared with a conventional SAR.

[1]  Soon-Jyh Chang,et al.  A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure , 2010, IEEE Journal of Solid-State Circuits.

[2]  Chih-Cheng Hsieh,et al.  A 0.4 V 1.94 fJ/conversion-step 10 bit 750 kS/s SAR ADC with Input-Range-Adaptive Switching , 2016, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Franco Maloberti,et al.  A 10-bit 100-MS/s Reference-Free SAR ADC in 90 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[4]  Jin-Yi Lin,et al.  A 0.3 V 10-bit 1.17 f SAR ADC With Merge and Split Switching in 90 nm CMOS , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.