Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic
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[1] Oliver Diessel,et al. Run-time compaction of FPGA designs , 1997, FPL.
[2] Mark de Wit,et al. A dynamic reconfiguration run-time system , 1997, Proceedings. The 5th Annual IEEE Symposium on Field-Programmable Custom Computing Machines Cat. No.97TB100186).
[3] Gordon J. Brebner,et al. A Virtual Hardware Operating System for the Xilinx XC6200 , 1996, FPL.
[4] Patrick Lysaght,et al. A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..
[5] Brad L. Hutchings,et al. Implementation Approaches for Reconfigurable Logic Applications , 1995, FPL.
[6] Juan Manuel Moreno,et al. Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor , 1997, FPL.