Linearity Test of Analog-to-Digital Converters Using Kalman Filtering

This work introduces an efficient code-density linearity testing algorithm for ADCs that can achieve high accuracy within short test time. The proposed algorithm uses Kalman filtering to suppress the effect of errors in the histogram counts based on characteristics of input noise and circuit mismatches. Appropriate versions of the algorithm for ADCs of flash and pipelined architectures are introduced respectively. Simulation results show that this approach can reduce the INLk estimation error by over 50% and achieve desired accuracy with a much smaller number of samples as compared to the conventional algorithm. Simulation and experimental results show that the proposed algorithm can significantly shorten the linearity test time by a factor of 10 or higher. Therefore, it can enable test and help maintain the quality of high-performance ADCs, and reduce the production test time and cost for medium and low resolution ADCs

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