Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores
暂无分享,去创建一个
Jorg Henkel | Jürgen Becker | Nadir Khan | Jorge Castro-Godinez | Shixiang Xue | J. Henkel | J. Becker | Jorge Castro-Godínez | Nadir Khan | Shixiang Xue
[1] Ingrid Verbauwhede,et al. Practical feasibility evaluation and improvement of a pay-per-use licensing scheme for hardware IP cores in Xilinx FPGAs , 2014, Journal of Cryptographic Engineering.
[2] Jürgen Becker,et al. Secure Local Configuration of Intellectual Property Without a Trusted Third Party , 2019, ARC.
[3] Jürgen Teich,et al. ReCoBus-Builder — A novel tool and technique to build statically and dynamically reconfigurable systems for FPGAS , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[4] Jim Tørresen,et al. Go Ahead: A Partial Reconfiguration Framework , 2012, 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines.
[5] Giorgio C. Buttazzo,et al. FLORA: FLoorplan Optimizer for Reconfigurable Areas in FPGAs , 2019, ACM Trans. Embed. Comput. Syst..
[6] Farinaz Koushanfar,et al. A Survey of Hardware Trojan Taxonomy and Detection , 2010, IEEE Design & Test of Computers.
[7] Mark Mohammad Tehranipoor,et al. A Survey on Chip to System Reverse Engineering , 2016, JETC.
[8] Brent E. Nelson,et al. RapidSmith 2: A Framework for BEL-level CAD Exploration on Xilinx FPGAs , 2015, FPGA.
[9] Chris Lavin,et al. RapidWright: Enabling Custom Crafted Implementations for FPGAs , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).
[10] Brent E. Nelson,et al. Vivado design interface: An export/import capability for Vivado FPGA designs , 2017, 2017 27th International Conference on Field Programmable Logic and Applications (FPL).
[11] Tim Güneysu,et al. Dynamic Intellectual Property Protection for Reconfigurable Devices , 2007, 2007 International Conference on Field-Programmable Technology.
[12] Peter M. Athanas,et al. OpenPR: An Open-Source Partial-Reconfiguration Toolkit for Xilinx FPGAs , 2011, 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and Phd Forum.
[13] Chip-Hong Chang,et al. A Pragmatic Per-Device Licensing Scheme for Hardware IP Cores on SRAM-Based FPGAs , 2014, IEEE Transactions on Information Forensics and Security.
[14] Jiliang Zhang,et al. A Practical Logic Obfuscation Technique for Hardware Security , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[15] Jürgen Becker,et al. A Secure Framework with Remote Configuration of Intellectual Property , 2019, ICISSP.
[16] Yan Feng,et al. Heterogeneous floorplanning for FPGAs , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[17] Chiara Sandionigi,et al. Automated Resource-Aware Floorplanning of Reconfigurable Areas in Partially-Reconfigurable FPGA Systems , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.
[18] Sorin A. Huss,et al. Bil: A tool-chain for bitstream reverse-engineering , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).
[19] Jean-Baptiste Note,et al. From the bitstream to the netlist , 2008, FPGA '08.
[20] Marco D. Santambrogio,et al. Wirelength driven floorplacement for FPGA-based partial reconfigurable systems , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).
[21] Brent E. Nelson,et al. RapidSmith: Do-It-Yourself CAD Tools for Xilinx FPGAs , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.
[22] Gang Qu,et al. Recent Attacks and Defenses on FPGA-based Systems , 2019, ACM Trans. Reconfigurable Technol. Syst..
[23] Jürgen Teich,et al. Power Signature Watermarking of IP Cores for FPGAs , 2008, J. Signal Process. Syst..
[24] Marco D. Santambrogio,et al. Floorplanning Automation for Partial-Reconfigurable FPGAs via Feasible Placements Generation , 2017, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[25] Xingming Sun,et al. A Chaotic IP Watermarking in Physical Layout Level Based on FPGA , 2011 .
[26] Miodrag Potkonjak,et al. Effective iterative techniques for fingerprinting design IP , 1999, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[27] Kizheppatt Vipin,et al. Architecture-Aware Reconfiguration-Centric Floorplanning for Partial Reconfiguration , 2012, ARC.
[28] Ingrid Verbauwhede,et al. A Pay-per-Use Licensing Scheme for Hardware IP Cores in Recent SRAM-Based FPGAs , 2012, IEEE Transactions on Information Forensics and Security.
[29] Tom Kean,et al. Cryptographic rights management of FPGA intellectual property cores , 2002, FPGA '02.
[30] Miodrag Potkonjak,et al. Fingerprinting techniques for field-programmable gate arrayintellectual property protection , 2001, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[31] Donald G. Bailey,et al. Connected components analysis of streamed images , 2008, 2008 International Conference on Field Programmable Logic and Applications.
[32] Brent E. Nelson,et al. Rapid prototyping tools for FPGA designs: RapidSmith , 2010, 2010 International Conference on Field-Programmable Technology.
[33] Mehdi B. Tahoori,et al. Checking for Electrical Level Security Threats in Bitstreams for Multi-tenant FPGAs , 2018, 2018 International Conference on Field-Programmable Technology (FPT).
[34] Tim Güneysu,et al. Generic Side-Channel Countermeasures for Reconfigurable Devices , 2011, CHES.
[35] Nilanjan Mukherjee,et al. On Test Points Enhancing Hardware Security , 2016, 2016 IEEE 25th Asian Test Symposium (ATS).
[36] Yongqiang Lyu,et al. A PUF-FSM Binding Scheme for FPGA IP Protection and Pay-Per-Device Licensing , 2015, IEEE Transactions on Information Forensics and Security.
[37] Thambipillai Srikanthan,et al. Ant Colony Optimization based Module Footprint Selection and Placement for Lowering Power in Large FPGA Designs , 2018, 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig).
[38] Akashi Satoh,et al. Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs , 2016, 2016 IEEE 5th Global Conference on Consumer Electronics.
[39] Chip-Hong Chang,et al. Public key protocol for usage-based licensing of FPGA IP cores , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).