Thermal/performance characterization of CMPs with 3D-stacked DRAMs under synergistic voltage-frequency control of cores and DRAMs

Chip-Multiprocessors (CMPs) with 3D-stacked DRAMs is promising for solving the memory wall problem, but the high power density makes 3D ICs frequently operate at or near the thermal limit. System hot spot of a CMP with 3D-stacked DRAMs is usually in DRAMs that are in the layers farthest from the heat sink. Heat from DRAMs and cores are all accumulated in DRAMs. Therefore, existing thermal managements for 3D ICs all perform thermal control on cores only because lowering the power-level of cores can also lower DRAM access frequency. However, as the power consumption of single DRAM access increases with the number of DRAM stacks and the width of the vertical links, the instantaneous DRAM accesses may easily overheat the system. So, in addition to lowering the access frequency of DRAMs, reducing the power consumption per DRAM access is also crucial. In this paper, we characterize the thermal and performance behavior of the target architecture when the voltage and frequency levels of cores and DRAMs are synergistically controlled. We also evaluate the thermal and performance behavior of existing thermal control methods that can be applied to the target architecture. The insights provided by the characterizations presented in this paper are important for developing an effective thermal management policy for CMPs with 3D-stacked DRAMs. Our results show that, synergistically controlling the voltage-frequency levels of cores and DRAMs does achieve higher thermal efficiency than controlling cores only.

[1]  Shunfei Chen,et al.  MARSS: A full system simulator for multicore x86 CPUs , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[2]  Li Shang,et al.  Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  John L. Henning.  SPEC CPU2006 benchmark descriptions , 2006, CARN.

[4]  Thomas F. Wenisch,et al.  MultiScale: memory system DVFS with multiple memory controllers , 2012, ISLPED '12.

[5]  Margaret Martonosi,et al.  Techniques for Multicore Thermal Management: Classification and New Exploration , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[6]  Kaustav Banerjee,et al.  A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[7]  Jie Meng,et al.  Optimizing energy efficiency of 3-D multicore systems with stacked DRAM under power and thermal constraints , 2012, DAC Design Automation Conference 2012.

[8]  Tajana Simunic,et al.  Energy efficient proactive thermal management in memory subsystem , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[9]  Christian Bienia,et al.  Benchmarking modern multiprocessors , 2011 .

[10]  Gabriel H. Loh,et al.  3D-Stacked Memory Architectures for Multi-core Processors , 2008, 2008 International Symposium on Computer Architecture.

[11]  Hsien-Hsin S. Lee,et al.  An optimized 3D-stacked memory architecture by exploiting excessive, high-density TSV bandwidth , 2010, HPCA - 16 2010 The Sixteenth International Symposium on High-Performance Computer Architecture.

[12]  Yusuf Leblebici,et al.  Dynamic thermal management in 3D multicore architectures , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[13]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[14]  Bruce Jacob,et al.  DRAMSim2: A Cycle Accurate Memory System Simulator , 2011, IEEE Computer Architecture Letters.

[15]  Thomas F. Wenisch,et al.  CoScale: Coordinating CPU and Memory System DVFS in Server Systems , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[16]  Qingyuan Deng,et al.  MemScale: active low-power modes for main memory , 2011, ASPLOS XVI.

[17]  Karthick Rajamani,et al.  What computer architects need to know about memory throttling , 2010, ISCA'10.

[18]  Zhao Zhang,et al.  Thermal modeling and management of DRAM memory systems , 2007, ISCA '07.

[19]  Gabriel H. Loh,et al.  Thermal analysis of a 3D die-stacked high-performance microprocessor , 2006, GLSVLSI '06.

[20]  Chia-Lin Yang,et al.  Exploring synergistic DVFS control of cores and DRAMs for thermal efficiency in CMPs with 3D-stacked DRAMs , 2013, ISLPED '13.