Power design challenges in deep-submicron technology

Power-efficient designs are becoming of increasing importance in the deep-submicron regime. Over the past decade, the reduction of dynamic power was the main focus in the design of power-efficient integrated circuits. However, as technology scales down, subthreshold and gate oxide leakage currents can no longer be neglected, arid must be taken into account in any design. Furthermore, the delivery of power to CMOS integrated circuits is facing increasing challenges in the deep-submicron regime. This paper investigates the challenges associated with designing power-efficient circuits as well as the delivery of power.

[1]  Yehea Ismail,et al.  Gasping the impact of on-chip inductance , 2001 .

[2]  Shin'ichiro Mutoh,et al.  1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.

[3]  Mark C. Johnson,et al.  Design and optimization of dual-threshold circuits for low-voltage low-power applications , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Jamil Kawa,et al.  Managing on-chip inductive effects , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Jacob K. White,et al.  Layout techniques for minimizing on-chip interconnect self-inductance , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[6]  Mohamed I. Elmasry,et al.  Multi-Threshold CMOS Digital Circuits , 2003 .

[7]  Rajendran Panda,et al.  Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing , 1999, DAC '99.

[8]  Yehia Massoud,et al.  On the accuracy of return path assumption for loop inductance extraction for 0.1 /spl mu/m technology and beyond , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..

[9]  R.Y. Chang,et al.  A highly manufacturable 0.25 /spl mu/m multiple-Vt dual gate oxide CMOS process for logic/embedded IC foundry technology , 1998, 1998 Symposium on VLSI Technology Digest of Technical Papers (Cat. No.98CH36216).

[10]  J. Burr,et al.  Optimization of quarter micron MOSFETs for low voltage/low power applications , 1995, Proceedings of International Electron Devices Meeting.

[11]  Mattan Kamon,et al.  Interconnect analysis: from 3-D structures to circuit models , 1999, DAC '99.

[12]  Satoshi Shigematsu,et al.  Power management technique for 1-V LSIs using embedded processor , 1996, Proceedings of Custom Integrated Circuits Conference.