Estimation of delay of signature sequences in coherent chip-asynchronous DS/SS systems

We consider the chip-asynchronous model for which the unknown delay of the received signature sequence is of the form (k+/spl epsiv/)T/sub c/, where k is an integer, /spl epsiv//spl isin/[0, 1) is the fractional delay, and T/sub c/ is the chip duration. We assume that a serial search scheme is used to obtain an estimate k/spl circ/ of k, and propose schemes which may be used to estimate /spl epsiv/ to any specified degree of accuracy simultaneously with the operation of the serial search. Such schemes may be useful in reducing the overall time to synchronization, because the code tracking loop will lock quickly if it is supplied with an accurate estimate of /spl epsiv/ (assuming that k/spl circ/=k). We have derived various estimators for /spl epsiv/, and in particular obtained an optimal estimator which is easily implementable and which has the best possible acquisition error probability performance, both in the average and minimax senses. Thus, it is possible to obtain an optimal estimate of /spl epsiv/ simultaneously with the operation of the serial search scheme, and at very little extra hardware cost. Some numerical results illustrating the performance of this optimal estimator are provided.<<ETX>>