Scheduling of behavioral VHDL by retiming techniques

In this paper we present a new approach to the scheduling of behavioral VHDL descriptions for controlow dominated applications containing a large number of nested conditionals and data dependent loops. The proposed algorithm is able to schedule and re-schedule descriptions for optimization subject to various cost functions. The timing of the I/O signals can be completely xed, partially xed or left to the scheduler. In this case the algorithm produces a schedule such that the number of clock cycles required for a complete execution of the behavioral description is minimized. Scheduling is performed as a behavioral VHDL code transformation and allows taking advantage of all the power of commercial RT synthesis systems. The corresponding problem is solved based on an analogy to the retiming problem on RT-level networks which can be solved in polynomial time. The e ciency of our approach is demonstrated on various examples.