Boundary scan test used at board level: moving towards reality

The author addresses the need for adapted design and test tools when using boundary scan in board-level circuit design and testing these assemblies. Test pattern generation is dealt with, the data flow around this generation software is discussed, and a format for test vectors is presented. Details are given for different approaches to test pattern generation, and a program for checking correctness of vectors is introduced. Also, a PC-based BST (boundary scan testing) validation tool capable of addressing the first needs of a designer is described. It is concluded that, although using BST pays off very rapidly, a lot of details in the total design and test trajectory have to be cleared up. Coupling between tools and availability of software capable of dealing with BST according to a selected strategy are items that have to be checked. >

[1]  Benoit Nadeau-Dostie,et al.  Testing of glue logic interconnects using boundary scan architecture , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[2]  Sue Vining Tradeoff decisions made for a P1149.1 controller design (ATE) , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[3]  Najmi T. Jarwala,et al.  A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[4]  R. E. Tulloss,et al.  BIST and boundary-scan for board level test: test program pseudocode , 1989, [1989] Proceedings of the 1st European Test Conference.

[5]  Alfred L. Crouch,et al.  Prototype testing simplified by scannable buffers and latches , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[6]  Vinod K. Agarwal,et al.  Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[7]  Najmi T. Jarwala,et al.  A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[8]  Paul Wagner,et al.  INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .