The research of interconnection network on coarse-grained reconfigurable Cipher Logic Array
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Wei Li | Yuanming Li | Min Liu | Yinjian Yan | Wei Li | Yuanming Li | Min Liu | Yinjian Yan
[1] Chulwoo Kim,et al. An On-Chip Network Fabric Supporting Coarse-Grained Processor Array , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[2] Li Wei,et al. A reconfigurable block cryptographic processor based on VLIW architecture , 2016, China Communications.
[3] Abdullah Atalar,et al. BilRC: An Execution Triggered Coarse Grained Reconfigurable Architecture , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[4] Leibo Liu,et al. REPROC: A Dynamically Reconfigurable Architecture for Symmetric Cryptography (Abstract Only) , 2015, FPGA.
[5] Fadi J. Kurdahi,et al. MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.
[6] Zhiyi Yu,et al. A 167-Processor Computational Platform in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.
[7] Rudy Lauwereins,et al. ADRES: An Architecture with Tightly Coupled VLIW Processor and Coarse-Grained Reconfigurable Matrix , 2003, FPL.
[8] Gerald Estrin,et al. Organization of Computer Systems-the Fixed Plus Variable Structure Computer , 1899 .