Specification-driven functional verification with Verilog PLI & VPI and SystemVerilog DPI

Verilog—through its Programming Language Interface (PLI) and Verilog Procedural Interface (VPI)—and SystemVerilog—through its Direct Programming Interface (DPI)—enable simulators to invoke user-defined C functions, which then verify some aspect of an instantiated Verilog or SystemVerilog design. This simulator-centric transfer of control inhibits specification-driven functional verification, where an executable specification verifies a design firsthand by progressively (1) applying a stimulus to the design, (2) simulating the design by temporarily transferring control to the simulator, and (3) verifying the design’s response to the applied stimulus. This thesis presents (1) a way to achieve specification-driven functional verification with Verilog PLI & VPI and SystemVerilog DPI; (2) a technique that eliminates unnecessary code coupling between a design and its executable specification; and (3) an application of these ideas using Verilog VPI and the Ruby programming language.

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