DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems

This paper presents DYNASTY–a new CAD framework aimed at supporting research of design techniques, algorithms and methodologies for dynamically reconfigurable logic (DRL) systems. Design flow implemented in the DYNASTY Framework is based around a temporal floorplanning (TF) DRL design abstraction, which allows simultaneous DRL design space exploration in spatial and temporal dimensions.

[1]  Majid Sarrafzadeh,et al.  3-D floorplanning: simulated annealing and greedy placement methods for reconfigurable computing systems , 1999, Proceedings Tenth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype (Cat. No.PR00246).

[2]  P. W. Foulk.  Data-folding in SRAM configurable FPGAs , 1993, [1993] Proceedings IEEE Workshop on FPGAs for Custom Computing Machines.

[3]  Patrick Lysaght.  Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic , 1997, FPL.

[4]  Patrick Lysaght,et al.  A simulation tool for dynamically reconfigurable field programmable gate arrays , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[5]  T. Kailath,et al.  VLSI and Modern Signal Processing , 1984 .

[6]  Milan Vasilko,et al.  Improving simulation accuracy in design methodologies for dynamically reconfigurable logic systems , 1999, Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375).

[7]  S. Holloway,et al.  Towards a consistent design methodology for run-time reconfigurable systems , 1999 .

[8]  Milan Vasilko,et al.  Architectural Synthesis Techniques for Dynamically Reconfigurable Logic , 1996, FPL.

[9]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[10]  Ranga Vemuri,et al.  Optimal temporal partitioning and synthesis for reconfigurable architectures , 1998, Proceedings Design, Automation and Test in Europe.

[11]  Reiner W. Hartenstein,et al.  Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.

[12]  P.G. Paulin,et al.  Algorithms for high-level synthesis , 1989, IEEE Design & Test of Computers.