论文信息 - A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

A sub-40 ns random-access chain FRAM architecture with a 768 cell-plate-line drive

This work demonstrates a prototype of nonvolatile chain ferroelectric RAM (chain FRAM), with fast compact cell-plate-line drive. A 16 kb chain FRAM test chip using 0.5 /spl mu/m 2-metal CMOS achieves 37 ns random-access time and 80 ns read/write cycle time at 3.3 V.

[1] Daisaburo Takashima,et al. High-density chain ferroelectric random access memory (chain FRAM) , 1997 .

[2] M. Fukuma,et al. A 60 ns 1 Mb nonvolatile ferroelectric memory with non-driven cell plate line write/read scheme , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.