A memory/adder model based on single C60 molecular transistors

A recent proposal, in which 1-bit memory cells and simple logic gates such as NOT and NOR gates were based on C60 molecules in an electromechanical grid acting as transistors, is extended to larger architectures. In order to meet the requirements of standard digital circuit architectures, some modifications have to be made compared to the original model. For example, the number of transistors has to be increased from two to thirteen for a single NOR gate to guarantee balanced logical levels. In the scheme employed to achieve this in the current work, all two-input gates, namely OR, AND and XOR gates, can be easily constructed using the same concept. These gates are then used to design a 1-bit full-adder and a clocked D-latch, which are then combined with the earlier proposed 1-bit memory cell as the basic constituents of a memory/adder model. Clocked signal transmissions, corresponding to the read process of two 2-bit words from memory cells, their movement through registers and finally their addition and passing the output through another register, are simulated using the electrical circuit software SPICE. For the design of this memory/adder circuit, 464 single C60 transistors are used.