论文信息 - NEW DESIGN OF LOW POWER 3T XOR CELL

NEW DESIGN OF LOW POWER 3T XOR CELL

This paper proposes a 3T XOR gate design implemented using pMOS transistors only. The design has been compared with existing design and significant improvement in power consumption has been obtained. All pre layout simulations are performed on 45nm standard model on Tanner EDA tool version 13.0.

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