A Low-Power Digit-Based Reconfigurable FIR Filter

In this brief, we present a digit-reconfigurable finite-impulse response (FIR) filter architecture with a very fine granularity. It provides a flexible yet compact and low-power solution to FIR filters with a wide range of precision and tap length. Based on the proposed architecture, an 8-digit reconfigurable FIR filter chip is implemented in a single-poly quadruple-metal 0.35-mum CMOS technology. Measurement results show that the fabricated chip operates up to 86 MHz when the filter draws 16.5 mW of power from a 2.5-V power supply

[1]  Joseph Mitola,et al.  The software radio architecture , 1995, IEEE Commun. Mag..

[2]  Yong Lian,et al.  A polynomial-time algorithm for designing FIR filters with power-of-two coefficients , 2002, IEEE Trans. Signal Process..

[3]  R. M. Hewlitt,et al.  Canonical signed digit representation for FIR digital filters , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).

[4]  K. Azadet,et al.  A low power 128-tap digital adaptive equalizer for broadband modems , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[5]  K. Muhammad,et al.  A 550-MSample/s 8-Tap FIR digital filter for magnetic recording read channels , 2000, IEEE Journal of Solid-State Circuits.

[6]  E. Buracchini,et al.  The software radio concept , 2000, IEEE Commun. Mag..

[7]  Kuk-Tae Hong,et al.  A high-speed programmable FIR digital filter using switching arrays , 1996, Proceedings of APCCAS'96 - Asia Pacific Conference on Circuits and Systems.

[8]  Mary Jane Irwin,et al.  ELM-A Fast Addition Algorithm Discovered by a Program , 1992, IEEE Trans. Computers.

[9]  Chao-Liang Chen,et al.  A trellis search algorithm for the design of FIR filters with signed-powers-of-two coefficients , 1999 .

[10]  Mitsuru Yamada,et al.  A high-speed FIR digital filter with CSD coefficients implemented on FPGA , 2001, ASP-DAC '01.

[11]  Jie Zhang,et al.  A high-speed, programmable, CSD coefficient FIR filter , 2002, IEEE Trans. Consumer Electron..

[12]  Jarkko Niittylahti,et al.  Adaptive FIR filter architectures for run-time reconfigurable FPGAs , 2002, 2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings..

[13]  Jun Rim Choi,et al.  Structured design of a 288-tap FIR filter by optimized partial product tree compression , 1997 .

[14]  A. Willson,et al.  A programmable FIR digital filter using CSD coefficients , 1996 .

[15]  V. Tapio,et al.  Software radio-an alternative for the future in wireless personal and multimedia communications , 1999, 1999 IEEE International Conference on Personal Wireless Communications (Cat. No.99TH8366).

[16]  L.J. Karam,et al.  Canonic signed digit Chebyshev FIR filter design , 2001, IEEE Signal Processing Letters.