A new hybrid topology for network on chip

With the advancements in semiconductor chip manufacturing technology, it has been possible to put the various components of a system with more than one hundred processors, on a single chip. Network on chip (NoC) has been used as an effective communication platform for such systems. Due to the delays induced by routers and other equipment employed in NoC, the performance of communications for chips using this architecture is usually less than that of bus based versions. It is expected that a combined solution can provide benefits of both. In this paper, with the goal of reducing delays associated with on-chip communications, five new hybrid topologies have been proposed. Then, a dominant topology has been selected among the candidates and a method for routing, based on dominant topology, has been provided. Simulation results are presented to evaluate the proposed methods.

[1]  William J. Dally,et al.  Route packets, not wires: on-chip inteconnection networks , 2001, DAC '01.

[2]  Tobias Bjerregaard,et al.  A survey of research and practices of Network-on-chip , 2006, CSUR.

[3]  Ranga Vemuri,et al.  A reconfigurable architecture for multicore systems , 2010, 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW).

[4]  Avinoam Kolodny,et al.  Best of both worlds: A bus enhanced NoC (BENoC) , 2010 .

[5]  Wayne H. Wolf,et al.  TGFF: task graphs for free , 1998, Proceedings of the Sixth International Workshop on Hardware/Software Codesign. (CODES/CASHE'98).

[6]  Kun-Lin Tsai,et al.  Design of low latency on-chip communication based on hybrid NoC architecture , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.

[7]  Radu Marculescu,et al.  Key research problems in NoC design: a holistic perspective , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[8]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[9]  Chita R. Das,et al.  A hybrid SoC interconnect with dynamic TDMA-based transaction-less buses and on-chip networks , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).

[10]  Chita R. Das,et al.  Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[11]  Chita R. Das,et al.  Network-on-Chip Architectures - A Holistic Design Exploration , 2010, Lecture Notes in Electrical Engineering.

[12]  Ravi Shankar,et al.  Survey of Network on Chip (NoC) Architectures & Contributions , 2009 .

[13]  Natalie D. Enright Jerger,et al.  Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Liu Zheng,et al.  Hybrid Communication Reconfigurable Network on Chip for MPSoC , 2010, 2010 24th IEEE International Conference on Advanced Information Networking and Applications.