CCE: A Combined SRAM and Non Volatile Cache for Endurance of Next Generation Multilevel Non Volatile Memories in Embedded Systems
暂无分享,去创建一个
[1] Fabrizio Lombardi,et al. A system-level scheme for resistance drift tolerance of a multilevel phase change memory , 2014, 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT).
[2] Greg Atwood,et al. Next-Generation Memory [Guest editors' introduction] , 2013, Computer.
[3] Fabrizio Lombardi,et al. A New Comprehensive Model of a Phase Change Memory (PCM) Cell , 2014, IEEE Transactions on Nanotechnology.
[4] James Cownie,et al. PinPlay: a framework for deterministic replay and reproducible analysis of parallel programs , 2010, CGO '10.
[5] Kartik Mohanram,et al. Reliable Nonvolatile Memories: Techniques and Measures , 2017, IEEE Design & Test.
[6] Dan Feng,et al. Increasing Lifetime and Security of Phase-Change Memory with Endurance Variation , 2016, 2016 IEEE 22nd International Conference on Parallel and Distributed Systems (ICPADS).
[7] Harish Patil,et al. Pin: building customized program analysis tools with dynamic instrumentation , 2005, PLDI '05.
[8] Puneet Gupta,et al. Comparative Evaluation of Spin-Transfer-Torque and Magnetoelectric Random Access Memory , 2016, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.
[9] Yuan Xie,et al. AdaMS: Adaptive MLC/SLC phase-change memory design for file storage , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).