Design and analysis of a WLAN CMOS power amplifier using multiple‐gated transistor technique

This article focused on 5.2 GHz highly integrated power amplifier for IEEE 802.11a WLAN application. Multiple-gated transistor technique was used to improve linearity. A new approach for choosing the bias voltage of auxiliary transistor by analyzing the shift of gate bias is used in the design. The simulated results of the proposed two-stage differential power amplifier indicate 25.28 dBm P1-dB, 32.87% PAE, and 26.18 dBm saturated output power with a 5.2 dB P1-dB improvement compared to conventional single transistor amplifier. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011. © 2011 Wiley Periodicals, Inc.

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