The Hybrid Architecture Parallel Fast Fourier Transform (HAPFFT)

THE HYBRID ARCHITECTURE PARALLEL FAST FOURIER

[1]  E. V. Jones,et al.  A pipelined FFT processor for word-sequential data , 1989, IEEE Trans. Acoust. Speech Signal Process..

[2]  C. Joanblanq,et al.  A fast single-chip implementation of 8192 complex point FFT , 1995 .

[3]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[4]  Behrooz Parhami,et al.  A class of parallel architectures for fast Fourier transform , 1996, Proceedings of the 39th Midwest Symposium on Circuits and Systems.

[5]  Alvin M. Despain,et al.  Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations , 1984, IEEE Transactions on Computers.

[6]  Winthrop W. Smith.  Handbook of Real-Time Fast Fourier Transforms , 1995 .

[7]  Brent E. Nelson,et al.  A Parallel FFT Architecture for FPGAs , 2004, FPL.

[8]  Yu Tai Ma,et al.  A VLSI-oriented parallel FFT algorithm , 1996, IEEE Trans. Signal Process..

[9]  E.E. Swartzlander,et al.  A radix 4 delay commutator for fast Fourier transform processor implementation , 1984, IEEE Journal of Solid-State Circuits.

[10]  Alexander A. Petrovsky,et al.  Multi-pipeline implementations of real-time vector DFT , 2004, Euromicro Symposium on Digital System Design, 2004. DSD 2004..

[11]  Richard G. Lyons,et al.  Understanding Digital Signal Processing , 1996 .

[12]  Brad L. Hutchings,et al.  JHDL-an HDL for reconfigurable systems , 1998, Proceedings. IEEE Symposium on FPGAs for Custom Computing Machines (Cat. No.98TB100251).

[13]  Jr. Earl E. Swartzlander,et al.  VLSI Signal Processing Systems , 1985 .

[14]  Susumu Horiguchi,et al.  WSI architecture of FFT , 1992, [1992] Proceedings International Conference on Wafer Scale Integration.

[15]  Bell Telephone.  A Fast Fourier Trans- form Algorithm for a Global, Highly Parallel Processor , 1969 .

[16]  Robert A. Collesidis,et al.  An ultra-high speed FFT processor , 1980, ICASSP.

[17]  J. Tukey,et al.  An algorithm for the machine calculation of complex Fourier series , 1965 .

[18]  Guoping Zhang,et al.  Parallel FFT with CORDIC for ultra wide band , 2004, 2004 IEEE 15th International Symposium on Personal, Indoor and Mobile Radio Communications (IEEE Cat. No.04TH8754).

[19]  Mats Torkelson,et al.  A new approach to pipeline FFT processor , 1996, Proceedings of International Conference on Parallel Processing.

[20]  Steve Gorman,et al.  Partial column FFT pipelines , 1995 .

[21]  A. A. Petrovsky,et al.  Multi-pipeline implementations of real-time vector DFT , 2004 .

[22]  Alvin M. Despain,et al.  Fourier Transform Computers Using CORDIC Iterations , 1974, IEEE Transactions on Computers.

[23]  A. W. M. van den Enden,et al.  Discrete Time Signal Processing , 1989 .

[24]  Brad L. Hutchings,et al.  A dynamic instruction set computer , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.

[25]  Yongjun Peng.  A parallel architecture for VLSI implementation of FFT processor , 2003, ASICON 2003.

[26]  Tom Chen,et al.  COBRA: a 100-MOPS single-chip programmable and expandable FFT , 1999, IEEE Trans. Very Large Scale Integr. Syst..

[27]  Marshall C. Pease,et al.  An Adaptation of the Fast Fourier Transform for Parallel Processing , 1968, JACM.

[28]  C. K. Yuen,et al.  Theory and Application of Digital Signal Processing , 1978, IEEE Transactions on Systems, Man, and Cybernetics.