Evolving challenges and techniques for nanometer SoC clock network synthesis

With continued technology scaling, increased variability effects and growing design complexity, the problem of clock network synthesis is becoming more challenging. In this paper, we discuss the key issues encountered while synthesizing the clock network. Furthermore, we present a clock tree resynthesis methodology to address some of the above challenges. It involves incremental modification on an already synthesized/routed clock tree for multi-corner multi-mode timing closure and has been validated on industrial designs using cutting-edge technology nodes.

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