论文信息 - A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi

A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi

A PRML read/write IC operating up to 450 Mbit/s is presented. The chip implements a 16-state EPR4 parity check time variant Viterbi detector and a digital servo. A 24/26 code with parity check improves the robustness to white noise, media noise and to off-track conditions. The device is integrated in a mature 0.35 /spl mu/m BiCMOS technology with a die size of 13 mm/sup 2/ (step and repeat) and dissipates 1.9 W (in read mode) at 450 Mbit/s.

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