Thermal-aware reliability analysis for Platform FPGAs

Increasing levels of integration in field programmable gate arrays, have resulted in high on-chip power densities, and temperatures. The heterogeneity of components and scaled feature sizes in platform FPGAs have made them vulnerable to various temperature dependent failure mechanisms. Hence, we need to introduce temperature awareness in tackling such failures that affect the lifetime reliability of FPGAs. In this paper, we present a dynamic thermal-aware reliability management (DTRM) framework to analyze the impact of temperature variations on the longterm/lifetime reliability of Platform FPGAs. We first study the temperature variations, both across and with-in designs, due to the use of various hard-blocks within a 65 nm platform FPGA. In the presence of such variations, we demonstrate the vulnerability of Platform FPGAs to two different hard-failures, namely, Electromigration, and time dependent dielectric breakdown (TDDB). We also analyze the performance degradation caused by Negative Bias Temperature Instability (NBTI) in the presence of thermal-variations. We validate the temperature variations estimated by the DTRM framework using a ring oscillator based real-time temperature measurement technique.

[1]  K. Tu.  Recent advances on electromigration in very-large-scale-integration of interconnects , 2003 .

[2]  Syed M. Alam,et al.  Design tool and methodologies for interconnect reliability analysis in integrated circuits , 2004 .

[3]  N. Vijaykrishnan,et al.  Thermal Characterization and Optimization in Platform FPGAs , 2006, 2006 IEEE/ACM International Conference on Computer Aided Design.

[4]  Vikas Chandra,et al.  Simultaneous optimization of driving buffer and routing switch sizes in an FPGA using an iso-area approach , 2002, Proceedings IEEE Computer Society Annual Symposium on VLSI. New Paradigms for VLSI Systems Design. ISVLSI 2002.

[5]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[6]  Narayanan Vijaykrishnan,et al.  Impact of NBTI on FPGAs , 2007, 20th International Conference on VLSI Design held jointly with 6th International Conference on Embedded Systems (VLSID'07).

[7]  Tim Tuan,et al.  Active leakage power optimization for FPGAs , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Yu Cao,et al.  An Integrated Modeling Paradigm of Circuit Reliability for 65nm CMOS Technology , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[9]  C. Capasso,et al.  Blech effect in single-inlaid Cu interconnects , 2001, Proceedings of the IEEE 2001 International Interconnect Technology Conference (Cat. No.01EX461).

[10]  P. Eaton,et al.  Soft error rate mitigation techniques for modern microcircuits , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[11]  Kevin Skadron,et al.  An Improved Block-Based Thermal Model in HotSpot 4.0 with Granularity Considerations , 2007 .

[12]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[13]  Sarita V. Adve,et al.  The impact of technology scaling on lifetime reliability , 2004, International Conference on Dependable Systems and Networks, 2004.

[14]  Yu Cao,et al.  An efficient method to identify critical gates under circuit aging , 2007, 2007 IEEE/ACM International Conference on Computer-Aided Design.