论文信息 - Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology

Impact of Passive & Active Load Gate Impedance on Breakdown Hardness in 28nm FDSOI Technology

The impact of integrated gate impedances, passive (polycomb, R<inf>G</inf>) and active (Input/Output MOSfet, Z<inf>load</inf>), on the breakdown (BD) behaviors of 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) transistors is discussed. It has been shown that R<inf>G</inf> and Z<inf>load</inf> affect directly the BD hardness of the devices. By reducing the BD hardness, a catastrophic failure of gate dielectric meaning complete loss of device functionalities can be avoided. Many configurations of R<inf>G</inf>, Z<inf>load</inf> are considered to obtain the best compromise in terms the BD hardness and functionalities of Device Under Test (DUT).

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