Automated Task Allocation for Network Processors

Network processors have great potential to combine high performance with increased flexibility. These multiprocessor systems consist of programmable elements, dedicated logic, and specialized memory and interconnection networks. However, the architectural complexity of the systems makes programming difficult. Programmers must be able to productively implement high performance applications for network processors to succeed. Ideally, designers describe applications in a domain specific language (DSL). DSLs expedite the development process by providing component libraries, communication and computation semantics, visualization tools, and test suites for an application domain. An integral aspect of mapping applications described in a DSL to network processors is allocating computational tasks to processing elements. We formulate this task allocation problem for a popular network processor, the Intel IXP1200. This method proves to be computationally efficient and produces results that are within 5% of aggregate egress bandwidths achieved by hand-tuned implementations on two representative applications: IPv4 forwarding and DiffServ.

[1]  Srinivas Devadas,et al.  Algorithms for hardware allocation in data path synthesis , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Fred Baker,et al.  Requirements for IP Version 4 Routers , 1995, RFC.

[4]  Armin Bender MILP based task mapping for heterogeneous multiprocessor systems , 1996, Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition.

[5]  Zheng Wang,et al.  An Architecture for Differentiated Services , 1998, RFC.

[6]  Eddie Kohler,et al.  The Click modular router , 1999, SOSP.

[7]  Hiroaki Ishii,et al.  Approximation algorithms for scheduling problems , 2000 .

[8]  Tami Tamir,et al.  Polynominal time approximation schemes for class-constrained packing problem , 2000, APPROX.

[9]  Robert Tappan Morris,et al.  Flexible Control of Parallelism in a Multiprocessor PC Router , 2001, USENIX Annual Technical Conference, General Track.

[10]  Ahmed Amine Jerraya,et al.  Programming models for network processors , 2001, International Symposium on Systems Synthesis.

[11]  Anand Srinivasan,et al.  Multiprocessor Scheduling in Processor-Based Router Platforms: Issues and Ideas , 2004 .

[12]  Andreas Kuehlmann,et al.  A fast pseudo-Boolean constraint solver , 2003, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.