Architecture-aware low-density parity-check codes
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[1] Ajay Dholakia,et al. Efficient implementations of the sum-product algorithm for decoding LDPC codes , 2001, GLOBECOM'01. IEEE Global Telecommunications Conference (Cat. No.01CH37270).
[2] Naresh R. Shanbhag,et al. Low-power VLSI decoder architectures for LDPC codes , 2002, ISLPED '02.
[3] John Cocke,et al. Optimal decoding of linear codes for minimizing symbol error rate (Corresp.) , 1974, IEEE Trans. Inf. Theory.
[4] Robert G. Gallager,et al. Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.
[5] Rüdiger L. Urbanke,et al. Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.
[6] Naresh R. Shanbhag,et al. Memory-efficient turbo decoder architectures for LDPC codes , 2002, IEEE Workshop on Signal Processing Systems.
[7] Andrew J. Blanksby,et al. Parallel decoding architectures for low density parity check codes , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).
[8] Naresh R. Shanbhag,et al. Turbo decoder architectures for low-density parity-check codes , 2002, Global Telecommunications Conference, 2002. GLOBECOM '02. IEEE.
[9] A. Glavieux,et al. Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.