PhaseNoC: TDM scheduling at the virtual-channel level for efficient network traffic isolation

The efficiency of modern Networks-on-Chip (NoC) is no longer judged solely by their physical scalability, but also by their ability to deliver high performance, Quality-of-Service (QoS), and flow isolation at the minimum possible cost. Although traditional architectures supporting Virtual Channels (VC) offer the resources for flow partitioning and isolation, an adversarial workload can still interfere and degrade the performance of other workloads that are active in a different set of VCs. In this paper, we present PhaseNoC, a truly non-interfering VC-based architecture that adopts Time-Division Multiplexing (TDM) at the VC level. Distinct flows, or application domains, mapped to disjoint sets of VCs are isolated, both inside the router's pipeline and at the network level. Any latency overhead is minimized by appropriate scheduling of flows in separate phases of operation, irrespective of the chosen topology. The resulting design yields significant reductions in the area/delay cost of the network. Experimental results corroborate that - with lower cost than state-of-the-art NoC architectures, and with minimum latency overhead - we remove any flow interference and allow for efficient network traffic isolation.

[1]  Jongman Kim,et al.  Centaur: a hybrid network-on-chip architecture utilizing micro-network fusion , 2014, Des. Autom. Embed. Syst..

[2]  Onur Mutlu,et al.  Kilo-NOC: A heterogeneous network-on-chip architecture for scalability and service guarantees , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[3]  Giorgos Dimitrakopoulos,et al.  Microarchitecture of Network-on-Chip Routers: A Designer's Perspective , 2014 .

[4]  Kees G. W. Goossens,et al.  Aelite: A flit-synchronous Network on Chip with composable and predictable services , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[5]  Jens Sparsø,et al.  Argo: A Time-Elastic Time-Division-Multiplexed NOC Using Asynchronous Routers , 2014, 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems.

[6]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[7]  Martin Schoeberl,et al.  A Statically Scheduled Time-Division-Multiplexed Network-on-Chip for Real-Time Systems , 2012, 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip.

[8]  Ying Gao,et al.  SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip , 2013, ISCA.

[9]  Kees G. W. Goossens,et al.  A TDM NoC supporting QoS, multicast, and fast connection set-up , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  William J. Dally,et al.  Virtual-channel flow control , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[11]  Natalie D. Enright Jerger,et al.  Novel Flow Control for Fully Adaptive Routing in Cache-Coherent NoCs , 2014, IEEE Transactions on Parallel and Distributed Systems.

[12]  Nan Jiang,et al.  Adaptive Backpressure: Efficient buffer management for on-chip networks , 2012, 2012 IEEE 30th International Conference on Computer Design (ICCD).

[13]  Krste Asanovic,et al.  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks , 2008, 2008 International Symposium on Computer Architecture.

[14]  AsanovicKrste,et al.  Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks , 2008 .