Full-chip analysis of leakage power under process variations, including spatial correlations

In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are -1.3% and -4.1%.

[1]  David Blaauw,et al.  Analysis and minimization techniques for total leakage considering gate oxide leakage , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[2]  Rajendran Panda,et al.  Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing , 1999, DAC '99.

[3]  Kaushik Roy,et al.  Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation , 2003, ISLPED '03.

[4]  Anantha Chandrakasan,et al.  Full-chip sub-threshold leakage power prediction model for sub-0.18 μm CMOS , 2002, ISLPED '02.

[5]  Norman C. Beaulieu,et al.  Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications , 1994, Proceedings of IEEE Vehicular Technology Conference (VTC).

[6]  David Blaauw,et al.  Statistical estimation of leakage current considering inter- and intra-die process variation , 2003, ISLPED '03.

[7]  Sachin S. Sapatnekar,et al.  Standby power optimization via transistor sizing and dual threshold voltage assignment , 2002, ICCAD 2002.

[8]  Dennis Sylvester,et al.  Tradeoffs between gate oxide leakage and delay for dual T/sub ox/ circuits , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  David Blaauw,et al.  Parametric yield estimation considering leakage variability , 2004, Proceedings. 41st Design Automation Conference, 2004..

[10]  Yuan Taur,et al.  Fundamentals of Modern VLSI Devices , 1998 .

[11]  Sachin S. Sapatnekar,et al.  Statistical timing analysis considering spatial correlations using a single PERT-like traversal , 2003, ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No.03CH37486).

[12]  J. Meindl,et al.  A circuit-level perspective of the optimum gate oxide thickness , 2001 .

[13]  David Blaauw,et al.  Modeling and analysis of leakage power considering within-die process variations , 2002, ISLPED '02.

[14]  S. Nassif,et al.  Delay variability: sources, impacts and trends , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).