Short-channel-effect-suppressed sub-0.1-/spl mu/m grooved-gate MOSFET's with W gate

Grooved-gate Si MOSFET's with tungsten gates are fabricated using conventional manufacturing technologies, and their short-channel-effect-free characteristics are verified down to a source and drain separation of around 0.1 /spl mu/m. Phase shift lithography followed by a side-wall oxide film formation technique achieves a spacing of less than 0.2 /spl mu/m between adjacent elevated polysilicons, subsequently resulting in a sub-0.1-/spl mu/m source and drain separation in the substrate. Short-channel effects, such as threshold voltage roll-off and punchthrough, are found to be completely suppressed. From device simulations, the potential barrier formed at each grooved-gate corner is considered to be responsible for the suppression of the short-channel effects. >

[1]  Eiji Takeda,et al.  A 5.9 mu m/sup 2/ super low power SRAM cell using a new phase-shift lithography , 1990, International Technical Digest on Electron Devices.

[2]  Hiroo Masuda,et al.  Grooved Gate MOSFET , 1977 .

[3]  K. Itoh,et al.  Simulation of sub-0.1- mu m MOSFETs with completely suppressed short-channel effect , 1993, IEEE Electron Device Letters.

[4]  J. Warnock,et al.  A Room Temperature 0.1 /spl mu/m CMOS on SOI , 1993, Symposium 1993 on VLSI Technology.

[5]  S. Asai,et al.  New grooved-gate MOSFET with drain separated from channel implanted region (DSC) , 1983, IEEE Transactions on Electron Devices.

[6]  T. Yoshitomi,et al.  An SPDD p-MOSFET structure suitable for 0.1 and sub 0.1 micron channel length and its electrical characteristics , 1992, 1992 International Technical Digest on Electron Devices Meeting.

[7]  Yuan Taur,et al.  High performance 0.1 /spl mu/m CMOS devices with 1.5 V power supply , 1993, Proceedings of IEEE International Electron Devices Meeting.

[8]  Digh Hisamoto,et al.  A 0.1 mu m-gate elevated source and drain MOSFET fabricated by phase-shifted lithography , 1991, International Electron Devices Meeting 1991 [Technical Digest].

[9]  C. Fiegna,et al.  Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junctions , 1993, Proceedings of IEEE International Electron Devices Meeting.

[10]  F. Masuoka,et al.  An analysis of the concave MOSFET , 1978, IEEE Transactions on Electron Devices.

[11]  R. R. Troutman,et al.  VLSI limitations from drain-induced barrier lowering , 1979 .

[12]  A New Capacitance Measurement Method For Lateral Diffusion Profiles In MOSFET's With Extremely Short Overlap Regions , 1993, Symposium 1993 on VLSI Technology.

[13]  Toru Toyabe,et al.  A sub-0.1-/spl mu/m grooved gate MOSFET with high immunity to short-channel effects , 1993, Proceedings of IEEE International Electron Devices Meeting.

[14]  M. Yanagisawa,et al.  Trench transistor cell with self-aligned contact (TSAC) for megabit MOS DRAM , 1986, 1986 International Electron Devices Meeting.

[15]  M. Kakumu,et al.  Design Methodology Of Deep Submicron CMOS Devices For 1V Operation , 1993, Symposium 1993 on VLSI Technology.

[16]  M. Sakao,et al.  A Straight-Line-Trench Isolation And Trench-Gate Transistor (SLIT) Cell For Giga-bit DRAMs , 1993, Symposium 1993 on VLSI Technology.

[17]  F. Masuoka,et al.  Double LDD concave (DLC) structure for sub-half micron MOSFET , 1988, Technical Digest., International Electron Devices Meeting.

[18]  Y. G. Wey,et al.  Room temperature 0.1 /spl mu/m CMOS technology with 11.8 ps gate delay , 1993, Proceedings of IEEE International Electron Devices Meeting.