Deep State Encryption for Sequential Logic Circuits

Logic encryption has been proposed as a potential solution to the hardware IP piracy problem. Naive logic encryption methods were shown to be susceptible to Boolean satisfiability (SAT) based attacks. In addition, the recently proposed Sequential SAT attack is able to decrypt many encrypted sequential logic circuits. This paper introduces a new logic encryption scheme that encrypts a sequential circuit on the occurrence of a chosen deep state. Two novel techniques to select a suitable deep state from the gate-level netlist of the design have been introduced. The attack resiliency of the proposed encryption technique against the sequential SAT attack is demonstrated using several standard benchmark circuits.

[1]  Marco Pistore,et al.  NuSMV 2: An OpenSource Tool for Symbolic Model Checking , 2002, CAV.

[2]  Siddharth Garg,et al.  Integrated Circuit (IC) Decamouflaging: Reverse Engineering Camouflaged ICs within Minutes , 2015, NDSS.

[3]  Ankur Srivastava,et al.  Mitigating SAT Attack on Logic Locking , 2016, CHES.

[4]  Sayak Ray,et al.  Evaluating the security of logic encryption algorithms , 2015, 2015 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[5]  Meng Li,et al.  AppSAT: Approximately deobfuscating integrated circuits , 2017, 2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[6]  Ujjwal Guin,et al.  Counterfeit Integrated Circuits , 2015 .

[7]  Jarrod A. Roy,et al.  Ending Piracy of Integrated Circuits , 2010, Computer.

[8]  Rohit Kapur,et al.  Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits , 2018, ArXiv.

[9]  Jeyavijayan Rajendran,et al.  Removal Attacks on Logic Locking and Camouflaging Techniques , 2020, IEEE Transactions on Emerging Topics in Computing.

[10]  Dick James,et al.  The state-of-the-art in semiconductor reverse engineering , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  David Z. Pan,et al.  Revisit sequential logic obfuscation: Attacks and defenses , 2017, 2017 IEEE International Symposium on Circuits and Systems (ISCAS).

[12]  Swarup Bhunia,et al.  HARPOON: An Obfuscation-Based SoC Design Methodology for Hardware Protection , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[13]  Jeyavijayan Rajendran,et al.  Fault Analysis-Based Logic Encryption , 2015, IEEE Transactions on Computers.

[14]  Jeyavijayan Rajendran,et al.  Security analysis of integrated circuit camouflaging , 2013, CCS.

[15]  John Villasenor,et al.  Chop shop electronics , 2013, IEEE Spectrum.

[16]  Jeyavijayan Rajendran,et al.  CamoPerturb: Secure IC camouflaging for minterm protection , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Vishwani D. Agrawal,et al.  Mutually disjoint signals and probability calculation in digital circuits , 1998, Proceedings of the 8th Great Lakes Symposium on VLSI (Cat. No.98TB100222).

[18]  Ranga Vemuri,et al.  On SAT-Based Attacks On Encrypted Sequential Logic Circuits , 2019, 20th International Symposium on Quality Electronic Design (ISQED).

[19]  L. H. Goldstein,et al.  SCOAP: Sandia Controllability/Observability Analysis Program , 1988, 17th Design Automation Conference.

[20]  Siddharth Garg,et al.  Reverse engineering camouflaged sequential circuits without scan access , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Ranga Vemuri,et al.  Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method , 2018, ACM Great Lakes Symposium on VLSI.

[22]  Ozgur Sinanoglu,et al.  SARLock: SAT attack resistant logic locking , 2016, 2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST).

[23]  Qiaoyan Yu,et al.  Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.