Low-voltage, high-speed CMOS analog latched voltage comparator using the "flipped voltage follower" as input stage

The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type's analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18@mm CMOS technology, and its measured performance shows 12-bit resolution at 20MHz comparison rate and 1V single supply voltage, with a total power consumption of 63.5@mW.

[1]  Piotr Otfinowski,et al.  A 2.5MS/s 225 µW 8-bit charge redistribution SAR ADC for multichannel applications , 2010, Proceedings of the 17th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2010.

[2]  William Redman-White.  A high bandwidth constant g/sub m/ and slew-rate rail-to-rail CMOS input circuit and its application to analog cells for low voltage VLSI systems , 1997 .

[3]  Mohamad Sawan,et al.  Low power/low voltage high speed CMOS differential track and latch comparator with rail-to-rail input , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).

[4]  Degang Chen,et al.  Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  Franco Maloberti.  Layout of analog and mixed analog-digital circuits , 1994 .

[6]  Pedro M. Figueiredo,et al.  Kickback noise reduction techniques for CMOS latched comparators , 2006, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  F. O. Eynde,et al.  A high-speed CMOS comparator with 8-b resolution , 1992 .

[8]  Hoi Lee.  A low-voltage low-power comparator With current-controlled dynamically-biased preamplifiers For DCM buck regulators , 2009, 2009 16th IEEE International Conference on Electronics, Circuits and Systems - (ICECS 2009).

[9]  Ramón González Carvajal,et al.  The flipped voltage follower: a useful cell for low-voltage low-power circuit design , 2005, IEEE Transactions on Circuits and Systems I: Regular Papers.

[10]  Gladys O. Ducoudray,et al.  High resolution low power 0.6µm CMOS 40MHz dynamic latch comparator , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[11]  José E. Franca,et al.  Design of Analog-Digital VLSI Circuits for Telecommunications and Signal Processing , 1993 .

[12]  M. Vertregt,et al.  CMOS technology for mixed signal ICs , 1997 .

[13]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[14]  Michel Steyaert,et al.  Custom analog low power design: the problem of low voltage and mismatch , 1997, Proceedings of CICC 97 - Custom Integrated Circuits Conference.

[15]  Satoshi Yamakawa,et al.  Low-current consumption CMOS comparator using charge-storage amplifier for A/D converters , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[16]  Hao-Chiao Hong,et al.  A 65-fJ/Conversion-Step 0.9-V 200-kS/s Rail-to-Rail 8-bit Successive Approximation ADC , 2007, IEEE Journal of Solid-State Circuits.

[17]  Paul M. Furth,et al.  On the design of low-power CMOS comparators with programmable hysteresis , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.