Compiler and System Techniques for soc Distributed Reconfigurable Accelerators

To answer new challenges, systems on chip need to gain flexi- bility and fpgas need to gain structure. We propose a general framework for SoC architectures and software tools in which different kind of pro- cessing units are programmed at high level. We show a reconfigurable unit suitable for this framework and we draw the outline of a super- compiler able to address such an architecture.

[1]  Stylianos Perissakis,et al.  Stream computations organized for reconfigurable execution , 2006, Microprocess. Microsystems.

[2]  Mateo Valero,et al.  Vector architectures: past, present and future , 1998, ICS '98.

[3]  Dean M. Tullsen,et al.  Simultaneous multithreading: Maximizing on-chip parallelism , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[4]  Christian Piguet,et al.  Low-Power Electronics Design , 2004 .

[5]  Jan M. Rabaey,et al.  Reconfigurable processing: the solution to low-power programmable DSP , 1997, 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[6]  Luciano Lavagno,et al.  Design space exploration for a wireless protocol on a reconfigurable platform , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[7]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[8]  Christoforos E. Kozyrakis,et al.  Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks , 2002, MICRO.

[9]  Stamatis Vassiliadis,et al.  The Molen Programming Paradigm , 2004, SAMOS.

[10]  John Wawrzynek,et al.  Stream Computations Organized for Reconfigurable Execution (SCORE) , 2000, FPL.

[11]  Corinne Ancourt,et al.  A Linear Algebra Framework for Static High Performance Fortran Code Distribution , 1997, Sci. Program..

[12]  Bernard Pottier,et al.  A LUT based high level synthesis framework for reconfigurable architectures , 2003 .

[13]  Bernard Pottier,et al.  Intermediate Level Components for Reconfigurable Platforms , 2004, SAMOS.

[14]  Reiner W. Hartenstein,et al.  Field-Programmable Logic Smart Applications, New Paradigms and Compilers , 1996, Lecture Notes in Computer Science.

[15]  David A. Patterson,et al.  Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..

[16]  Corinne Ancourt,et al.  How to Add a New Phase in PIPS: the Case of Dead Code Elimination , 1996 .