Testing of Fault-Tolerant Hardware Through Partial Control of Inputs

The problem of testing fault-tolerant redundant digital systems is investigated. To test redundant systems through normal voter outputs, independent control of the output of each replicated unit is required. In the past it was assumed that independent control of the output of a replicated unit requires independent control of all of its inputs. The authors show that partial control of inputs is actually required. The critical input set problem, which is the problem of finding a set of inputs that need to be independently controlled, is formulated. Solutions are offered for different testing strategies, including exhaustive testing and deterministic testing, and for different levels of circuit description. >

[1]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[2]  Anthony S. Wojcik,et al.  A General, Constructive Approach to Fault-Tolerant Design Using Redundancy , 1989, IEEE Trans. Computers.

[3]  Robert K. Brayton,et al.  Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[4]  David S. Johnson,et al.  Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .

[5]  Michael Nicolaidis,et al.  Self-exercising checkers for unified built-in self-test (UBIST) , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  J. Taylor,et al.  Switching and finite automata theory, 2nd ed. , 1980, Proceedings of the IEEE.

[7]  Edward A. Feigenbaum,et al.  Switching and Finite Automata Theory: Computer Science Series , 1990 .

[8]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[9]  Irith Pomeranz,et al.  COMPACTEST: a method to generate compact test sets for combinational circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Charles E. Stroud,et al.  Design for testability and test generation for static redundancy system level fault-tolerant circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[11]  Irith Pomeranz,et al.  COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS , 1991, 1991, Proceedings. International Test Conference.