(Abstract )This paper introduces the development of Field Programmable Gate Array(FPGA), and evaluates the usability of FPGA devices which include the use of reconfigurable logic, Block RAM(BRAM), I/O resources, Digital Signal Processor(DSP) hard core, the selection of CPU soft core/hard core and the usable clock frequencies. It predicts future trend in the ever quest for high performance FPGA. It suggests not using slice resource more than 85 %, selecting better supported tool company for soft/hard core and let all I/O signal buffered by registers. (Key words )Field Programmable Gate Array(FPGA); usability evaluation; reconfigurable logic; CPU soft core/hard core; Digital Signal Processor (DSP) hard core DOI: 10.3969/j.issn.1000-3428.2011.13.093