D trigger resisting single event upset

The invention discloses a D trigger resisting single event upset, and aims to improve the single event upset resistance of the D trigger. The D trigger comprises a clock circuit, a main latch, a slave latch, a first phase inverter circuit and a second phase inverter circuit. the main latch comprises 10 PMOS (P-channel Metal Oxide Semiconductor) tubes and 10 NMOS (N-Mental-Oxide-Semiconductor) tubes; the slave latch comprises 10 PMOS tubes and 10 NMOS tubes; both the main latch and the slave latch adopt bimodule redundant reinforcement; and in the main latch and the slave latch, C2MOS circuits are also improved, that is, pull-up PMOS tubes and pull-down NMOS tubes in redundant relation in each C2MOS circuit are separated. The D trigger has strong single event upset resistance, is suitable for standard cell library for a reinforced integrated circuit resisting single event upset, and is used in the fields of aviation, aerospace, and the like.