Establishing latch correspondence for sequential circuits using distinguishing signatures

This paper addresses the problem of establishing the unknown correspondence for the latch variables of two sequential circuits which have the same state encoding. This has direct application in finite state machine verification: If a one-to-one correspondence can be established between the latches of two circuits, then checking for their equivalence reduces to a much simpler combinational equivalence check problem. The approach presented in this paper is based on methods used to solve the unknown correspondence problem for inputs and outputs in combinational circuits. It computes input and novel latch output signatures, using ROBDDs, for each latch variable of a circuit that help to establish correspondence. Experimental results on a large set of benchmarks show the efficacy of this approach.

[1]  Irith Pomeranz,et al.  On diagnosis and correction of design errors , 1993, ICCAD.

[2]  Sharad Malik,et al.  Limits of using signatures for permutation independent Boolean comparison , 1995, ASP-DAC '95.

[3]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[4]  Robert K. Brayton,et al.  Incremental FSM Re-encoding for Simplifying Verification by Symbolic Traversal , 1995 .

[5]  Michael Weber,et al.  Detection of symmetry of Boolean functions represented by ROBDDs , 1993, ICCAD '93.

[6]  Sharad Malik,et al.  Permutation and phase independent Boolean comparison , 1993, Integr..

[7]  Randal E. Bryant,et al.  Efficient implementation of a BDD package , 1991, DAC '90.

[8]  Irith Pomeranz,et al.  On diagnosis and correction of design errors , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).

[9]  Masahiro Fujita,et al.  Spectral Transforms for Large Boolean Functions with Applications to Technology Mapping , 1997, Formal Methods Syst. Des..

[10]  M. Marek-Sadowska,et al.  Verifying equivalence of functions with unknown input correspondence , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[11]  Massoud Pedram,et al.  Boolean matching using binary decision diagrams with applications to logic synthesis and verification , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.