An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling

Power and bandwidth requirements have become more stringent for DRAMs in recent years. This is largely because mobile devices (such as smart phones) are more intensively relying on the use of graphics. Current DDR memory I/Os operate at 5Gb/s with a power efficiency of 17.4mW/Gb/s (i.e., 17.4pJ/b)[1], and graphic DRAM I/Os operate at 7Gb/s/pin [3] with a power efficiency worse than that of DDR. High-speed serial links [5], with a better power efficiency of ∼1mW/Gb/s, would be favored for mobile memory I/O interface. However, serial links typically require long initialization time (∼1000 clock cycles), and do not meet mobile DRAM I/O requirements for fast switching between active, standby, self-refresh and power-down operation modes [4]. Also, traditional baseband-only (or BB-only) signaling tends to consume power super-linearly [4] for extended bandwidth due to the need of power hungry pre-emphasis, and equalization circuits.

[1]  Michael Bucher,et al.  A 4.3 GB/s Mobile Memory Interface With Power-Efficient Bandwidth Scaling , 2010, IEEE Journal of Solid-State Circuits.

[2]  Jae-Hyung Lee,et al.  A 7 Gb/s/pin 1 Gbit GDDR5 SDRAM With 2.5 ns Bank to Bank Active Time and No Bank Group Restriction , 2011, IEEE Journal of Solid-State Circuits.

[3]  Young-Hyun Jun,et al.  A 6Gb/s/pin pseudo-differential signaling using common-mode noise rejection techniques without reference signal for DRAM interfaces , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Young-Hyun Jun,et al.  A 5-Gb/s/pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme , 2009, IEEE Journal of Solid-State Circuits.

[5]  Jae-Hyung Lee,et al.  A 7Gb/s/pin GDDR5 SDRAM with 2.5ns bank-to-bank active time and no bank-group restriction , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[6]  Goichi Ono,et al.  A 12.3mW 12.5Gb/s complete transceiver in 65nm CMOS , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[7]  Sung-Woo Shin,et al.  A 3.6 Gb/s/pin simultaneous bidirectional (SBD) I/O interface for high-speed DRAM , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).