A 0.5-3.5 Gb/s low-power low-jitter serial data CMOS transceiver
暂无分享,去创建一个
R. Gu | J.M. Tran | Heng-Chih Lin | Ah-Lyan Yee | M. Izzard
[1] R. Mactaggart,et al. A 1.0625 Gbps transceiver with 2x-oversampling and transmit signal pre-emphasis , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.
[2] Deog-Kyoon Jeong,et al. A CMOS Serial Link for Fully Duplexed Data Communication(Special Issue on the 1994 VLSI Circuits Symposium) , 1995 .
[3] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.